A Design of PLL with a Process-Immune Locking-in Monitor and Reduce Jitter
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چکیده
A PLL circuit includes phase detector for detecting phase error between an input and output signal of the PLL circuit and outputting pump up and pump down signal. A charge pump generates a charge pump signal in response to pump up and pump down signals. A loop filter filters charge pump signal to generate a filtered signal. A boost-up device coupled to loop filter output terminal charges a loop filter input terminal, to expedite the filtered signal reaching predetermined voltage level. A VCO coupled loop filter output terminal and the phase detector generates output signal. A common mode voltage reaching lock-in time is reduced by boost-up device charging loop filter to expedite filtered signal reaching common mode voltage, when filtered signal is lower than predetermined detecting voltage.
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